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| LTC4558 Dual SIM/Smart Card Power Supply and Interface FEATURES DESCRIPTION The LTC(R)4558 provides the power conversion and signal level translation needed for advanced cellular telephones to interface with 1.8V or 3V subscriber identity modules (SIMs). The device meets all requirements for 1.8V and 3V SIMs and contains LDO regulators to power 1.8V or 3V SIM cards from a 2.7V to 5.5V input. The output voltages can be set using the two voltage selection pins and up to 50mA of load current can be supplied. A channel select pin determines which channel is open for communication. Separate enable pins for each channel allow both cards to be powered at once and allow for faster transition from one channel to the other. Internal level translators allow controllers operating with supplies as low as 1.4V to interface with 1.8V or 3V Smart Cards. Battery life is maximized by a low operating current of 65A and a shutdown current of less than 1A. Board area is minimized by the low profile 3mm x 3mm x 0.75mm leadless QFN package. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Protected by U.S. Patents, including 6356140. Power Management and Control for Two SIM Cards or Smart Cards Independent 1.8V/3V VCC Control for Both Cards Supports Simultaneous Powering of Both Cards Fast Channel Switching Automatic Level Translation Dynamic Pull-Ups Deliver Fast Signal Rise Times* Built-In Fault Protection Circuitry Automatic Activation/Deactivation Sequencing Circuitry Low Operating/Shutdown Current > 10kV ESD on SIM Card Pins Meets EMV Fault Tolerance Requirements Low Profile 20-Lead (3mm x 3mm) QFN Package APPLICATIONS GSM, TD-SCDMA and other 3G+ Cellular Phones Wireless Point-of-Sale Terminals Multiple SIM Card Interfaces TYPICAL APPLICATION DVCC VBATT 1.4V TO 4.4V 3V TO 6V DVCC 0.1F DVCC CLKIN RSTIN DATA CLKRUNA CONTROLLER CLKRUNB GND ENABLEA ENABLEB CSEL VSELA VSELB LTC4558 VCCB CLKB RSTB I/OB 1F C1 C3 C2 C7 VCC CLK RST I/O GND C5 4558 TA01 0.1F VBATT I/OA RSTA CLKA VCCA 1F C7 C2 C3 CLK C1 VCC I/O RST 1.8V/3V SIM CARD A GND C5 Deactivation Sequence RSTX 5V/DIV CLKX 5V/DIV I/OX 5V/DIV VCCX 2V/DIV CVCCX = 1F 10s/DIV 4558 TA02 1.8V/3V SIM CARD B 4558f 1 LTC4558 ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE/ORDER INFORMATION TOP VIEW ENABLEB RSTIN VSELB 15 CLKRUNB 14 CLKRUNA 21 13 CSEL 12 VSELA 11 ENABLEA 6 RSTA 7 I/OA 8 DATA 9 10 CLKIN RSTB CLKB VCCB 1 DVCC 2 VBATT 3 VCCA 4 CLKA 5 I/OB VBATT, DVCC, DATA, RSTIN, CLKIN, CLKRUNA, CLKRUNB, ENABLEA, ENABLEB, CSEL, VSELA, VSELB to GND ............................................. -0.3V to 6V I/OA, CLKA, RSTA ........................ -0.3V to VCCA + 0.3V I/OB, CLKB, RSTB ........................ -0.3V to VCCB + 0.3V ICCA,B (Note 4) .......................................................80mA VCCA,B Short-Circuit Duration ........................... Indefinite Operating Temperature Range (Note 3) ...-40C to 85C Storage Temperature Range...................-65C to 125C 20 19 18 17 16 UD PACKAGE 20-LEAD (3mm x 3mm) PLASTIC QFN TJMAX = 125C, JA = 68C/W, JC = 4.2C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER PART NUMBER LTC4558EUD UD PART MARKING LCSH Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS PARAMETER Input Power Supply VBATT Operating Voltage IVBATT Operating Current DVCC Operating Voltage IDVCC Operating Current IDVCC Shutdown Current IVBATT Shutdown Current SIM Card Supplies VCCA,B Output Voltage VCCA,B Turn-On Time Channel Switching Time DVCC = 0V CONDITIONS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBATT = 3.3V, DVCC = 1.8V, CA = CB = 1F, unless otherwise specified. MIN TYP MAX 5.5 UNITS V A A V A A A V V ms s 2.7 65 65 1.4 6 0.1 0.1 2.85 1.71 3.00 1.8 0.8 1 VCCA = 3V, VCCB = 0V, ICCA = 0A VCCA = 1.8V, VCCB = 0V, ICCA = ICCB = 0A 100 100 5.5 10 1 1 3.15 1.89 1.5 3V Mode, 0mA < ICCA,B < 50mA 1.8V Mode, 0mA < ICCA,B < 30mA ICCA,B = 0mA, ENABLEA,B to VCCA,B at 90% Selected Voltage ENABLEA = ENABLEB = RSTIN = DVCC CSEL to RSTB 4558f 2 LTC4558 ELECTRICAL CHARACTERISTICS PARAMETER CLKA,B Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Rise/Fall Time CLKA,B Frequency RSTA,B Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Rise/Fall Time I/OA, I/OB Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Rise/Fall Time Short-Circuit Current DATA Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Rise/Fall Time Low Input Threshold (VIL) High Input Threshold (VIH) Input Current (IIH/IIL) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: This specification applies to both Smart Card classes. Sink Current = - 500A (VI/OA,B = 0V) Source Current = 20A (VI/OA,B = VCCA,B) Loaded with 50pF (10% to 90%) The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBATT = 3.3V, DVCC = 1.8V, CA = CB = 1F, unless otherwise specified. CONDITIONS Sink Current = - 200A (Note 2) Source Current = 200A (Note 2) Loaded with 50pF (10% to 90%) (Note 2) (Note 2) Sink Current = - 200A (Note 2) Source Current = 200A (Note 2) Loaded with 50pF (10% to 90%) (Note 2) Sink Current = - 1mA (VDATA = 0V) (Note 2) Source Current = 20A (VDATA = VDVCC) (Note 2) Loaded with 50pF (10% to 90%) (Note 2) VDATA = 0V (Note 2) MIN TYP MAX 0.2 UNITS V V VCCA,B -0.2 16 10 0.2 VCCA,B -0.2 100 0.3 0.85 * VCCA,B 500 5 10 0.3 0.8 * DVCC 125 500 0.15 * DVCC 0.85 * DVCC -1 1 ns MHz V V ns V V ns mA V V ns V V A ENABLEA, ENABLEB, RSTIN, CLKIN, CSEL, VSELA, VSELB, CLKRUNA, CLKRUNB Note 3: The LTC4558E is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 4: Based on long-term current density limitations. 4558f 3 LTC4558 TYPICAL PERFORMANCE CHARACTERISTICS No Load Supply Current vs VBATT 100 95 VBATT SUPPLY CURRENT (A) 90 85 80 75 70 65 60 55 50 2.7 3.1 3.9 4.3 4.7 5.1 VBATT SUPPLY VOLTAGE (V) 3.5 5.5 4.0 -40 0 -15 35 10 TEMPERATURE (C) 60 85 4557 G02 TA = 25C unless otherwise noted. VBATT Quiescent Current (IVBATT - ICC) vs Load Current 250 VBATT QUIESCENT CURRENT (A) TA = 25C VBATT = 3.1V I/OX Short-Circuit Current vs Temperature 7.0 6.5 6.0 5.5 5.0 4.5 VDVCC = VBATT = 5.5V VCCX = 3V I/OX SHORTED TO VCCX TA = 25C ICCA = ICCB = 0A SHORT-CIRCUIT CURRENT (mA) 200 DROPOUT 150 VCCX = 3V 100 VCCX = 1.8V 50 10 100 1000 10000 LOAD CURRENT (A) 100000 4557 G03 4557 G01 VBATT Shutdown Current vs Supply Voltage 4.0 VBATT SHUTDOWN CURRENT (A) 3.5 DVCC SHUTDOWN CURRENT (A) TA = -40C 3.0 2.5 2.0 1.5 1.0 0.5 0 2.7 3.1 5.1 4.7 3.5 3.9 4.3 VBATT SUPPLY VOLTAGE (V) 5.5 TA = 25C TA = 85C 0.5 0.4 0.3 0.2 0.1 0 VDVCC = 1.8V 0.6 DVCC Shutdown Current vs Supply Voltage VBATT = 5.5V TA = -40C TO 85C 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 DVCC SUPPLY VOLTAGE (V) 4557 G05 4557 G04 4558f 4 LTC4558 TYPICAL PERFORMANCE CHARACTERISTICS Data - I/O Channel, CL = 40pF I/0X 1V/DIV TA = 25C unless otherwise noted. DATA 1V/DIV 200ns/DIV 4557 G06 Deactivation Sequence, CVCCX = 1F RSTX 5V/DIV CLKX 5V/DIV I/OX 5V/DIV VCCX 2V/DIV 20s/DIV 4557 G07 4558f 5 LTC4558 PIN FUNCTIONS DVCC (Pin 2): Power. Reference voltage for the control logic. VBATT (Pin 3): Power. Supply voltage for the analog sections of the LTC4558. VCCA,VCCB (Pins 4, 1): Card Socket. The VCCA,VCCB pins should be connected to the VCC pins of the respective card sockets. The activation of the VCCA,VCCB pins are controlled by ENABLEA and ENABLEB. They can be set to 1.8V or 3V via the VSELA and VSELB inputs. CLKA,CKLB (Pins 5, 20): Card Socket. The CLKA,CKLB pins should be connected to the CLK pins of the respective card sockets. The CLKA,CKLB signals are derived from the CLKIN pin. They provide a level shifted CLKIN signal to the selected card. The CLKA,CKLB pins are gated off until VCCA,VCCB attain their correct values. When a card socket is deselected, its CLK pin may be left active or brought LOW using the CLKRUNA, CLKRUNB pins. RSTA,RSTB (Pins 6, 19): Card Socket. The RSTA,RSTB pins should be connected to the RST pins of the respective card sockets. The RSTA,RSTB signals are derived from the RSTIN pin. When a card is selected, its RST pin follows RSTIN. The RSTA,RSTB pins are gated off until VCCA,VCCB attain their correct values. When a card socket is deselected, the state of its RST pin is latched to its current state. I/OA,I/OB (Pins 7, 18): Card Socket. The I/OA,I/OB pins should be connected to the I/O pins of the respective card sockets. When a card is selected, its I/O pin transmits/receives data to/from the DATA pin. The I/OA,I/OB pins are gated off until VCCA,VCCB attain their correct values. DATA (Pin 8): Input/Output. Microcontroller side data I/O pin. The DATA pin provides the bidirectional communication path to both cards. One of the cards may be selected to communicate via the DATA pin at a time. The pin possesses a weak pull-up current source, allowing the controller to use an open drain output and maintain a HIGH state during shutdown, as long as DVCC is powered. RSTIN (Pin 9): Input. The RSTIN pin supplies the reset signal to the cards. It is level shifted and transmitted directly to the RST pin of the selected card. CLKIN (Pin 10): Input. The CLKIN pin supplies the clock signal to the cards. It is level shifted and transmitted directly to the CLK pin of the selected card. If CLKRUNA,B is HIGH, the clock signal will be transmitted to the CLKA,B pin, regardless of whether that card is selected, as long as that card socket is enabled. ENABLEA, ENABLEB (Pins 11, 17): Inputs. The ENABLEA and ENABLEB pins enable or disable channel A and channel B, respectively. VSELA, VSELB (Pins 12, 16): Inputs. The VSELA and VSELB pins select the voltage level of each set of SIM/ Smart Card pins. Bringing either of these pins HIGH will set the output level of its respective channel to 3V. Bringing either of these pins LOW will set the output level of its respective channel to 1.8V. CSEL (Pin 13): Input. The CSEL pin selects which set of SIM/Smart Card pins are active. CLKRUNA, CLKRUNB (Pins 14, 15): Inputs. The CLKRUNA and CLKRUNB inputs are used to select whether the clock signal is always sent to card sockets that are enabled or whether the clock is gated with the CSEL pin. Exposed Pad (Pin 21): Ground. This ground pad must be soldered directly to a PCB ground plane. 4558f 6 LTC4558 BLOCK DIAGRAM DVCC 2 VBATT 3 VCCA 4 LDOA LDOB 1 VCCB DVCC I/OA 7 18 I/OB RSTA 6 19 RSTB CLKA 5 20 CLKB CLKRUNA 14 DATA 8 RSTIN 9 CLKIN 10 DVCC 15 CLKRUNB CONTROL LOGIC 21 GND 13 CSEL 12 11 16 17 ENABLEB VSELA ENABLEA VSELB 4558 BD 4558f 7 LTC4558 OPERATION The LTC4558 features two independent SIM/Smart Card channels. Only one of these channels may be open for communication at a time however both channels can be enabled and made ready for communication using the ENABLEA and ENABLEB pins. This allows faster transition from one channel to the other. Each channel is able to produce two voltage levels, 1.8V and 3V. The channel selection and voltage selection are controlled by the CSEL, VSELA and VSELB pins as shown in the table below: Table 1. Channel and Voltage Truth Table CSEL 0 0 0 0 1 1 1 1 VSELA 0 0 1 1 0 0 1 1 VSELB 0 1 0 1 0 1 0 1 SELECTED CARD A A A A B B B B VOLTAGES A B 1.8V 1.8V 3V 3V 1.8V 1.8V 3V 3V 1.8V 3V 1.8V 3V 1.8V 3V 1.8V 3V BIDIRECTIONAL PIN dv dt ISTART Dynamic Pull-Up Current Sources The current sources on the bidirectional pins (DATA,I/OA,B) are dynamically activated to achieve a fast rise time with a relatively small static current. Once a bidirectional pin is relinquished, a small start-up current begins to charge the node. An edge rate detector determines if the pin is released by comparing its slew rate with an internal reference value. If a valid transition is detected, a large pull-up current enhances the edge rate on the node. The higher slew rate corroborates the decision to charge the node thereby affecting a dynamic form of hysteresis. LOCAL SUPPLY + - VREF 4558 F01 Figure 1. Dynamic Pull-Up Current Source Bidirectional Channels The bidirectional channels are level shifted to the appropriate VCCA,B voltages at the I/OA,B pins. An NMOS pass transistor performs the level shifting. The gate of the NMOS transistor is biased such that the transistor is completely off when both sides have relinquished the channel. If one side of the channel asserts a LOW, then the transistor will convey the LOW to the other side. Note that current passes from the receiving side of the channel to the transmitting side. The low output voltage of the receiving side will be dependent upon the voltage at the transmitting side plus the IR drop of the pass transistor. When a card socket is selected, it becomes a candidate to drive data on the DATA pin and likewise receive data from the DATA pin. When a card socket is deselected, its I/O pin will be pulled HIGH and communication with the DATA pin will be disabled. If both channels are disabled, a weak pull-up ensures that the DATA pin is held HIGH, as long as DVCC is powered. Reset Channels When a card is selected, the reset channel provides a level shifted path from the RSTIN pin to the RST pin of the selected card. When a card is deselected, the last state of the RSTA,B pin is latched. This allows a deselected card to remain active, and therefore eliminates delays associated with card initialization. Clock Run Mode Various SIM/Smart Cards may have different requirements for the state of the clock pin when the channel is not open for communication. The CLKRUNA,B pins allow the user to select whether the clock is brought LOW after the channel is deselected or allowed to run. If a channel is enabled, bringing its CLKRUN pin HIGH will transmit the clock to the corresponding card socket, whether or not the channel is selected using the CSEL. 4558f 8 LTC4558 OPERATION Activation/Deactivation Activation and deactivation sequencing is handled by builtin circuitry. Each channel may be activated or deactivated independently of the other. The activation sequence for each channel is initiated by bringing the ENABLEA,B pin HIGH. The activation sequence is outlined below: 1. The RSTA,B, CLKA,B and I/OA,B pins are held LOW. 2. VCCA,B is enabled. 3. After VCCA,B is stable at its selected level, the I/OA,B and RSTA,B channels are enabled. 4. The clock channel is enabled on the rising edge of the second clock cycle after the I/OA,B pin is enabled. The deactivation sequence is initiated by bringing the ENABLEA,B pin LOW. The deactivation sequence is outlined below: 1. The reset channel is disabled and RSTA,B is brought LOW. 2. The clock channel is disabled and the CLKA,B pin is brought LOW two clock cycles after ENABLEA,B is brought LOW. If the clock is not running, the clock channel will be disabled approximately 9s after the ENABLEA,B pin is brought LOW. 3. The I/O channel is disabled and the I/OA,B pin is brought LOW approximately 9s after the ENABLEA,B pin is brought LOW. 4. VCCA,B will be depowered after the I/OA,B pin is brought LOW. The activation or deactivation sequences will take place every time a card channel is enabled or disabled. When a channel is deselected using the CSEL pin, the RSTA,B state is latched, the I/OA,B channel becomes high impedance and CLKA,B is brought LOW after a maximum of two clock cycles. Fault Detection The VCCA,B, I/OA,B, RSTA,B, CLKA,B and DATA pins are all protected against short-circuit faults. While there are no logic outputs to indicate that a fault has occurred, these pins will be able to tolerate the fault condition until it has been removed. The VCCA,B, I/OA,B, and RSTA,B pins possess fault protection circuitry which will limit the current available to the pins. Each VCC pin is capable of supplying approximately 90mA (typ) before the output voltage is reduced. The CLKA,B pins are designed to tolerate faults by reducing the current drive capability of their output stages. After a fault is detected by the internal fault detection logic, the logic waits for a fault detection delay to elapse before reducing the current drive capability of the output stage. The reduced current drive allows the LTC4558 to detect when the fault has been removed. 4558f 9 LTC4558 APPLICATIONS INFORMATION 10kV ESD Protection All Smart Card pins (CLKA,B, RSTA,B, I/OA,B, VCCA,B and GND) can withstand over 10kV of human body model ESD in-situ. In order to ensure proper ESD protection, careful board layout is required. The GND pin should be tied directly to a ground plane. The VCCA,B capacitors should be located very close to the VCCA,B pins and tied immediately to the ground plane. Capacitor Selection A total of four capacitors is required to operate the LTC4558. An input bypass capacitor is required at VBATT and DVCC. Output bypass capacitors are required on each of the Smart Card VCC pins. There are several types of ceramic capacitors available, each having considerably different characteristics. For example, X7R ceramic capacitors have excellent voltage and temperature stability but relatively low packing density. Y5V and X5R ceramic capacitors have apparently higher packing density but poor performance over their rated voltage or temperature ranges. Under certain voltage and temperature conditions Y5V, X5R and X7R ceramic capacitors can be compared directly by case size rather than specified value for a desired minimum capacitance. The VCCA,B outputs should be bypassed to GND with a 1F capacitor. A low ESR ceramic capacitor is recommended on each VCC pin to ensure ESD compliance. VBATT and DVCC should be bypassed with 0.1F ceramic capacitors. Compliance Testing Inductance due to long leads on type approval equipment can cause ringing and overshoot that leads to testing problems. Small amounts of capacitance and damping resistors can be included in the application without compromising the normal electrical performance of the LTC4558 or Smart Card system. Generally a 100 resistor and a 20pF capacitor will accomplish this, as shown in Figure 2. 1F LTC4558 VCCA,B CLKA,B RSTA,B 100 I/OA,B 20pF 4558 F02 100 100 20pF 20pF 20pF SMART CARD SOCKET Figure 2. Additional Components for Improved Compliance Testing 4558f 10 LTC4558 PACKAGE DESCRIPTION UD Package 20-Lead Plastic QFN (3mm x 3mm) (Reference LTC DWG # 05-08-1720 Rev A) 0.70 0.05 3.50 0.05 (4 SIDES) 1.65 0.05 2.10 0.05 PACKAGE OUTLINE 0.20 0.05 0.40 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED BOTTOM VIEW--EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 0.25 x 45 CHAMFER 19 20 0.40 0.10 1 2 1.65 0.10 (4-SIDES) 3.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.05 TYP R = 0.115 TYP (UD20) QFN 0306 REV A 0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.20 0.05 0.40 BSC 4558f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC4558 TYPICAL APPLICATION DVCC VBATT 1.4V TO 4.4V 3V TO 6V DVCC C3 0.1F C4 0.1F C7 C2 C3 CLK C1 C1 1F GND ENABLEA ENABLEB CSEL VSELA VCCB CLKB RSTB C2 1F C1 C3 C2 C7 VCC CLK RST I/O GND C5 4558 TA01a DVCC CLKIN RSTIN DATA CLKRUNA VBATT I/OA RSTA CLKA VCCA I/O RST 1.8V/3V SIM CARD A GND C5 VCC CONTROLLER CLKRUNB 1.8V/3V SIM CARD B I/OB VSELB LTC4558 RELATED PARTS PART NUMBER LTC1555L/ LTC1555L-1.8 LTC1555/LTC1556 LTC1755/LTC1756 DESCRIPTION 1MHz, SIM Power Supply and Level Translator for 1.8V/3V/5V SIM Cards 650kHz, SIM Power Supply and Level Translator for 3V/5V SIM Cards 850kHz, Smart Card Interface with Serial Control for 3V/5V Smart Card Applications Dual Smart Card Interface with Serial Control for 1.8V/3V/5V Smart Card Applications 900kHz, SIM Power Supply for 3V/5V SIM Cards COMMENTS VIN: 2.6V to 6.6V, VOUT = 1.8V/3V/5V, IQ = 32A, ISD < 1A, SSOP16 VIN: 2.7V to 10V, VOUT = 3V/5V, IQ = 60A, ISD < 1A, SSOP16, SSOP20 VIN: 2.7V to 7V, VOUT = 3V/5V, IQ = 60A, ISD < 1A, SSOP16, SSOP24 LTC1955 VIN: 3V to 5.5V, VOUT = 1.8V/3V/5V, IQ = 200A, ISD < 1A, QFN32 LTC1986 LTC4555 LTC4556 LTC4557 VIN: 2.6V to 4.4V, VOUT = 3V/5V, IQ = 14A, ISD < 1A, ThinSOT SIM Power Supply and Level Translator VIN: 3V to 6V, VOUT = 1.8V/3V, IQ = 40A, ISD < 1A, QFN16 for 1.8V/3V SIM Cards Smart Card Interface with Serial Control Dual SIM/Smart Card Power Supply and Level Translator for 1.8V/3V Cards VIN: 2.7V to 5.5V, VOUT = 1.8V/3V/5V, IQ = 250A, ISD < 1A, 4 x 4 QFN24 VIN: 2.7V to 5.5V, VOUT = 1.8V/3V, IQ = 250A, ISD < 1A, QFN16 ThinSOT is a trademark of Linear Technology Corporation. 4558f 12 Linear Technology Corporation (408) 432-1900 FAX: (408) 434-0507 LT 0107 * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2007 |
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